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1500 mhz to 2500 mhz quadrature modulator adl5372 rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2006 analog devices, inc. all rights reserved. features output frequency range: 1500 mhz to 2500 mhz modulation bandwidth: >500 mhz (3 db) 1 db output compression: 14 dbm @ 1900 mhz noise floor: ?158 dbm/hz sideband suppression: ?45 dbc @ 1900 mhz carrier feedthrough: ?45 dbm @ 1900 mhz single supply: 4.75 v to 5.25 v 24-lead lfcsp_vq applications cellular communication systems cdma2000/gsm/wcdma wimax/broadband wireless access systems satellite modems functional block diagram ibbp ibbn vout loip loin qbbn qbbp quadrature phase splitter 06511-001 figure 1. general description the adl5372 is a member of the fixed-gain quadrature modulator (f-mod) family designed for use from 1500 mhz to 2500 mhz. its excellent phase accuracy and amplitude balance enable high performance intermediate frequency or direct radio frequency modulation for communication systems. the adl5372 provides a >500 mhz, 3 db baseband bandwidth, making it ideally suited for use in broadband zero if or low if-to-rf applications and in broadband digital predistortion transmitters. the adl5372 accepts two differential baseband inputs and a single-ended, local oscillator (lo) and generates a single- ended output. the adl5372 is fabricated using the analog devices, inc. advanced silicon-germanium bipolar process. it is available in a 24-lead, exposed-paddle, pb-free, lfcsp. performance is specified over a ?40c to +85c temperature range. a pb-free evaluation board is available.
adl5372 rev. 0 | page 2 of 24 table of contents features .............................................................................................. 1 applications....................................................................................... 1 functional block diagram .............................................................. 1 general description ......................................................................... 1 revision history ............................................................................... 2 specifications..................................................................................... 3 absolute maximum ratings............................................................ 5 esd caution.................................................................................. 5 pin configuration and function descriptions............................. 6 typical performance characteristics ............................................. 7 theory of operation ...................................................................... 11 circuit description..................................................................... 11 basic connections .......................................................................... 12 optimization ............................................................................... 13 applications information .............................................................. 14 dac modulator interfacing ..................................................... 14 limiting the ac swing .............................................................. 14 filtering........................................................................................ 14 using the ad9779 auxiliary dac for carrier feedthrough nulling ......................................................................................... 15 gsm operation .......................................................................... 15 wcdma operation .................................................................. 16 wimax operation .................................................................... 16 lo generation using plls ....................................................... 16 transmit dac options ............................................................. 17 modulator/demodulator options ........................................... 17 evaluation board ............................................................................ 18 characterization setup .................................................................. 19 outline dimensions ....................................................................... 21 ordering guide .......................................................................... 21 revision history 12/06revision 0: initial version
adl5372 rev. 0 | page 3 of 24 specifications v s = 5 v; t a = 25c; lo = 0 dbm 1 single-ended; baseband i/q amplitude = 1.4 v p-p di fferential sine waves in quadrature with a 500 mv dc bias; baseband i/q frequency (f bb ) = 1 mhz, unless otherwise noted. table 1. parameter conditions min typ max unit operating frequency range low frequency 1500 mhz high frequency 2500 mhz lo = 1900 mhz output power v iq = 1.4 v p-p differential 7.1 dbm output p1db 14.2 dbm carrier feedthrough ?45 dbm sideband suppression ?45 dbc quadrature error 0.21 degrees i/q amplitude balance 0.09 db second harmonic p out ? (f lo + (2 f bb )), p out = 6.2 dbm ?50 dbc third harmonic p out ? (f lo + (3 f bb )), p out = 6.2 dbm ?47 dbc output ip2 f1 bb = 3.5 mhz, f2 bb = 4.5 mhz, p out = 1 dbm per tone 54 dbm output ip3 f1 bb = 3.5 mhz, f2 bb = 4.5 mhz, p out = 1 dbm per tone 27 dbm noise floor i/q inputs = 0 v differential wi th a 500 mv common-mode bias, 20 mhz carrier offset; lo = 1960 mhz ?158 dbm/hz gsm 6 mhz carrier offset, p out = 5 dbm, p lo = 6 dbm; lo = 1960 mhz ?158 dbc/hz wcdma single carrier, 20 mhz carrier offset, p out = ?10 dbm, p lo = 0 dbm; lo = 1966 mhz ?157.6 dbm/hz lo = 2150 mhz output power v iq = 1.4 v p-p differential 7.2 dbm outputp1db 14 dbm carrier feedthrough ?41 dbm sideband suppression ?44 dbc quadrature error 0.27 degrees i/q amplitude balance 0.12 db second harmonic p out ? (f lo + (2 f bb )), p out = 6.2 dbm ?59 dbc third harmonic p out ? (f lo + (3 f bb )), p out = 6.2 dbm ?48 dbc output ip2 f1 bb = 3.5 mhz, f2 bb = 4.5 mhz, p out = 1 dbm per tone 65 dbm output ip3 f1 bb = 3.5 mhz, f2 bb = 4.5 mhz, p out = 1 dbm per tone 26.5 dbm noise floor i/q inputs = 0 v differential wi th a 500 mv common-mode bias, 20 mhz carrier offset ?158 dbm/hz wcdma single carrier, 20 mhz carrier offset, p out = ?10 dbm, p lo = 0 dbm; lo = 2140 mhz ?157.5 dbm/hz lo = 2400 mhz output power v iq = 1.4 v p-p differential 5.6 dbm outputp1db 12.4 dbm carrier feedthrough ?36 dbm sideband suppression ?40 dbc quadrature error 0.6 degrees i/q amplitude balance 0.13 db second harmonic p out ? (f lo + (2 f bb )), p out = 6.2 dbm ?54 dbc third harmonic p out ? (f lo + (3 f bb )), p out = 6.2 dbm ?48 dbc output ip2 f1 bb = 3.5 mhz, f2 bb = 4.5 mhz, p out = 1 dbm per tone 57 dbm output ip3 f1 bb = 3.5 mhz, f2 bb = 4.5 mhz, p out = 1 dbm per tone 24.5 dbm noise floor i/q inputs = 0 v differential wi th a 500 mv common-mode bias, 20 mhz carrier offset; lo = 2350 mhz ?158.5 dbm/hz wimax 10 mhz carrier bandwidth (256 subcarriers), 64 qam signal, 70 mhz carrier offset, p out = ?10 dbm, p lo = 0 dbm; lo = 2350 mhz ?158 dbm/hz
adl5372 rev. 0 | page 4 of 24 parameter conditions min typ max unit lo inputs lo drive level 1 characterization performed at typical level ?6 0 +6 dbm input return loss see figure 9 for a plot of return loss vs. frequency ?12 db baseband inputs pin ibbp, pin i bbn, pin qbbp, pin qbbn i and q input bias level 500 mv input bias current current sourcing from ea ch baseband input with a bias of 500 mv dc 2 45 a input offset current 0.1 a differential input impedance 2900 k bandwidth (0.1 db) lo = 1900 mhz, baseband input = 700 mv p-p sine wave on 500 mv dc 70 mhz bandwidth (1 db) lo = 1900 mhz, baseband input = 700 mv p-p sine wave on 500 mv dc 350 mhz power supplies pin vps1 and pin vps2 voltage 4.75 5.25 v supply current 165 ma 1 high lo drive reduces noise at a 6 mhz carrier offset in gsm applications. 2 see v-to-i converter section for architecture information.
adl5372 rev. 0 | page 5 of 24 absolute maximum ratings table 2. parameter rating supply voltage vpos 5.5 v ibbp, ibbn, qbbp, qbbn 0 v to 2 v loip and loin 13 dbm internal power dissipation 1100 mw ja (exposed paddle soldered down) 54c/w maximum junction temperature 150c operating temperature range ?40c to +85c storage temperature range ?65c to +150c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution
adl5372 rev. 0 | page 6 of 24 pin configuration and fu nction descriptions f-mod top view (not to scale) com1 vps1 com1 vps1 vps1 vps1 vps5 vps3 vps4 vps2 vps2 vout 1 3 2 4 5 6 18 16 17 15 14 13 com2 loin loip com2 com3 com3 qbbp com4 qbbn com4 ibbn ibbp 7 9 8 10 11 12 24 22 23 21 20 19 06511-002 figure 2. pin configuration table 3. pin function descriptions pin o. mnemonic description 1, 2, 7, 10 to 12, 21, 22 com1 to com4 input common pins. connect to ground plane via a low impedance path. 3 to 6, 14 to 18 vps1 to vps5 positive supply voltage pins. all pins should be connected to the same supply (v s ). to ensure adequate external bypassing, connect 0.1 f capacitors between each pin and ground. adjacent power supply pins of the same name can share one capacitor (see figure 25 ). 8, 9 loip, loin 50 single-ended local oscillator input. internally dc-biased. pins must be ac-coupled. ac-couple loin to ground and drive lo through loip. 13 vout device output. single-ended rf output. pin sh ould be ac-coupled to the load. the output is ground referenced. 19, 20, 23, 24 ibbp, ibbn, qbbn, qbbp differential in-phase and quadrature baseban d inputs. these high impedance inputs must be dc-biased to 500 mv dc and must be driven from a low impedance source. nominal characterized ac signal swing is 700 mv p-p on each pin. this results in a differential drive of 1.4 v p-p with a 500 mv dc bias. these inputs are not self-biased and must be externally biased. exposed paddle connect to ground plane via a low impedance path.
adl5372 rev. 0 | page 7 of 24 typical performance characteristics v s = 5 v; t a = 25c; lo = 0 dbm single-ended; baseband i/q amplitude = 1. 4 v p-p differential sine waves in quadrature with a 500 mv dc bias; baseband i/q frequency (f bb ) = 1 mhz, unless otherwise noted. 0 1 2 3 4 5 6 7 8 9 1500 1600 1700 1800 1900 2000 2100 2200 2300 2400 2500 06511-003 lo frequency (mhz) ssb output power (dbm) t a = ?40c t a = +25c t a = +85c figure 3. single sideband (ssb) output power (p out ) vs. lo frequency (f lo ) and temperature 0 1 2 3 4 5 6 7 8 9 1500 1600 1700 1800 1900 2000 2100 2200 2300 2400 2500 06511-004 lo frequency (mhz) ssb output power (dbm) v s = 5v v s = 5.25v v s = 4.75v figure 4. single sideband (ssb) output power (p out ) vs. lo frequency (f lo ) and supply 5 0 ?5 1 10 100 1000 output power variance (db) baseband frequency (mhz) 06511-005 figure 5. i and q input bandwidth normalized to gain @ 1 mhz (f lo = 1900 mhz) 0 2 4 6 8 10 12 14 16 1500 1600 1700 1800 1900 2000 2100 2200 2300 2400 2500 06511-006 lo frequency (mhz) output p1db (dbm) t a = +85c t a = +25c t a = ?40c figure 6. ssb output p1db co mpression point (op1db) vs. f lo and temperature 0 2 4 6 8 10 12 14 16 1500 1600 1700 1800 1900 2000 2100 2200 2300 2400 2500 06511-007 lo frequency (mhz) output p1db (dbm) v s = 4.75v v s = 5.25v v s = 5v figure 7. ssb output p1db compression point (op1db) vs. f lo and supply 06511-043 0 180 30 330 60 90 270 300 120 240 150 210 2500mhz 1500mhz 1500mhz 2500mhz s11 of loip s22 of output figure 8. smith chart of loip s11 and vout s22 (f lo from 1600 mhz to 2500 mhz)
adl5372 rev. 0 | page 8 of 24 ?25 ?20 ?15 ?10 ?5 0 1500 1600 1700 1800 1900 2000 2100 2200 2300 2400 2500 0 6511-009 lo frequency (mhz) return loss (db) figure 9. return loss (s11) of loip ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 1500 1600 1700 1800 1900 2000 2100 2200 2300 2400 2500 06511-010 lo frequency (mhz) carrier feedthrough (dbm) t a = +85c t a = ?40c t a = +25c figure 10. carrier feedthrough vs. f lo and temperature multiple devices shown ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 1500 1600 1700 1800 1900 2000 2100 2200 2300 2400 2500 0 6511-040 lo frequency (mhz) carrier feedthrough (dbm) t a = +85c t a = ?40c t a = +25c figure 11. carrier feedthrough vs. f lo and temperature after nulling at 25c multiple devices shown ?60 ?50 ?40 ?30 ?20 ?10 0 1500 1600 1700 1800 1900 2000 2100 2200 2300 2400 2500 06511-012 lo frequency (mhz) sideband suppression (dbc) t a = +85c t a = ?40c t a = +25c figure 12. sideband suppression vs. f lo and temperature multiple devices shown ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 1500 1600 1700 1800 1900 2000 2100 2200 2300 2400 2500 06511-041 lo frequency (mhz) sideband suppression (dbc) t a = +85c t a = ?40c t a = +25c figure 13. sideband suppression vs. f lo and temperature after nulling at 25c multiple devices shown ?80 ?70 ?60 ?50 ?40 ?30 ? 20 0.20.61.01.41.82.22.63.03.4 second-order distortion, third-order distortion, carrier feedthrough, sideband suppression ?15 ?10 ?5 0 5 10 15 ssb output power (dbm) 06511-014 baseband input voltage (v p?p) ssb output power (dbm) sideband suppression (dbc) third order (dbc) second order (dbc) carrier feedthrough (dbm) figure 14. second- and third-order distortion, carrier feedthrough, sideband suppression, and ssb p out vs. baseband differential input level (f lo = 1900 mhz)
adl5372 rev. 0 | page 9 of 24 ?80 ?70 ?60 ?50 ?40 ?30 ? 20 0.20.61.01.41.82.22.63.03.4 second-order distortion, third-order distortion, carrier feedthrough, sideband suppr ession ?15 ?10 ?5 0 5 10 15 ssb output power (dbm) 06511-015 baseband input voltage (v p-p) ssb output power (dbm) sideband suppr ession (dbc) third order (dbc) second order (dbc) carrier feedthrough (dbm) figure 15. second- and third-order distortion, carrier feedthrough, sideband suppression, and ssb p out vs. baseband differential input level (f lo = 2150 mhz) ? 20 ?80 1500 2500 second-order and third-orde r distortion (dbc) lo frequency (mhz) 06511-016 ?70 ?60 ?50 ?40 ?30 1600 1700 1800 1900 2000 2100 2200 2300 2400 second order t a = ?40c second order t a = +25c second order t a = +85c third order t a = +85c third order t a = ?40c third order t a = +25c figure 16. second- and thir d-order distortion vs. f lo and temperature (baseband i/q amplitude = 1.4 v p-p differential) ?60 ?55 ?50 ?45 ?40 ?35 ?30 ?25 ? 20 1m 10m 100m 4 4.5 5 5.5 6 6.5 7 7.5 8 ssb output power (dbm) second-order distortion, third-order distortion, carrier feedthrough, sideband suppression 0 6511-017 baseband frequency (hz) ssb output power (dbm) sideband suppression (dbc) third order (dbc) second order (dbc) carrier feedthrough (dbm) figure 17. second- and third-order distortion, carrier feedthrough, sideband suppression, and ssb p out vs. f bb and temperature (f lo = 1900 mhz) 0 5 10 15 20 25 30 1500 1600 1700 1800 1900 2000 2100 2200 2300 2400 2500 06511-018 lo frequency (mhz) output third-order intercept (dbm) t a = +25c t a = ?40c t a = +85c figure 18. oip3 vs. fr equency and temperature 0 10 20 30 40 50 60 70 80 1500 1600 1700 1800 1900 2000 2100 2200 2300 2400 2500 0 6511-019 lo frequency (mhz) output second-order intercept (dbm) t a = +25c t a = ?40c t a = +85c figure 19. oip2 vs. fr equency and temperature second-order distortion, third-order distortion, carrier feedthrough, sideband suppression ?70 ?60 ?50 ?40 ?30 ? 20 ?6 ?4 ?2 0 2 4 6 3 4 5 6 7 8 ssb output power (dbm) 06511-020 lo amplitude (dbm) sideband suppression (dbc) third order (dbc) second order (dbc) carrier feedthrough (dbm) ssb output power (dbm) figure 20. second- and third-order distortion, carrier feedthrough, sideband suppression, and ssb p out vs. lo amplitude (f lo = 1900 mhz)
adl5372 rev. 0 | page 10 of 24 second-order distortion, third-order distortion, carrier feedthrough, sideband suppression ?70 ?60 ?50 ?40 ?30 ? 20 ?6?4?20246 3 4 5 6 7 8 ssb output power (dbm) 06511-021 lo amplitude (dbm) ssb output power (dbm) sideband suppression (dbc) third order (dbc) second order (dbc) carrier feedthrough (dbm) figure 21. second- and third-order distortion, carrier feedthrough, sideband suppression, and ssb p out vs. lo amplitude (f lo = 2150 mhz) 0.10 0.11 0.12 0.13 0.14 0.15 0.16 0.17 0.18 0.19 0.20 ?40 ?15 10 35 60 85 v s = 4.75v v s = 5.25v v s = 5v 06511-042 temperature (c) supply current (a) figure 22. power supply current vs. temperature 06511-023 noise at 20mhz offset (dbm/hz) quantity 0 2 4 6 8 10 12 14 16 18 20 22 ?159.1 ?158.7 ?158.3 ?157.9 ?157.5 ?157.1 ?158.9 ?158.5 ?158.1 ?157.7 ?157.3 f lo = 1960mhz figure 23. 20 mhz offset no ise floor distribution at f lo = 1960 mhz (i/q amplitude = 0 mv p-p with 500 mv dc bias)
adl5372 rev. 0 | page 11 of 24 theory of operation circuit description overview the adl5372 can be divided into five circuit blocks: the lo interface, the baseband voltage-to-current (v-to-i) converter, the mixers, the differential-to-single-ended (d-to-s) stage, and the bias circuit. a detailed block diagram of the device is shown in figure 24 . phase splitter out loip loin ibbp ibbn qbbp qbbn 0 6511-024 figure 24. block diagram the lo interface generates two lo signals in quadrature. these signals are used to drive the mixers. the i and q baseband input signals are converted to currents by the v-to-i stages, which then drive the two mixers. the outputs of these mixers combine to feed the output balun, which provides a single-ended output. the bias cell generates reference currents for the v-to-i stage. lo interface the lo interface consists of a polyphase quadrature splitter followed by a limiting amplifier. the lo input impedance is set by the polyphase. the lo can be driven either single-ended or differentially. when driven single-ended, the loin pin should be ac grounded via a capacitor. each quadrature lo signal then passes through a limiting amplifier that provides the mixer with a limited drive signal. v-to-i converter the differential baseband inputs (qbbp, qbbn, ibbn, and ibbp) consist of the bases of pnp transistors, which present a high impedance. the voltages applied to these pins drive the v-to-i stage that converts baseband voltages into currents. the differential output currents of the v-to-i stages feed each of their respective gilbert-cell mixers. the dc common-mode voltage at the baseband inputs sets the currents in the two mixer cores. varying the baseband common-mode voltage influences the current in the mixer and affects overall modulator performance. the recommended dc voltage for the baseband common-mode voltage is 500 mv dc. mixers the adl5372 has two double-balanced mixers: one for the in-phase channel (i-channel) and one for the quadrature channel (q-channel). both mixers are based on the gilbert-cell design of four cross-connected transistors. the output currents from the two mixers sum together into a load. the signal developed across this load is used to drive the d-to-s stage. d-to-s stage the output d-to-s stage consists of an on-chip balun that converts the differential signal to a single-ended signal. the balun presents high impedance to the output (vout). hence, a matching network may be needed at the output for optimal power transfer. bias circuit an on-chip band gap reference circuit is used to generate a proportional-to-absolute temperature (ptat) reference current for the v-to-i stage.
adl5372 rev. 0 | page 12 of 24 basic connections figure 25 shows the basic connections for the adl5372. vps5 vps3 vps4 vps2 vps2 vout com2 loin loip com2 com3 com3 qbbp com4 qbbn com4 ibbn ibbp com1 vps1 com1 vps1 vps1 vps1 1 2 3 4 5 6 18 17 16 15 14 13 vout c13 0.1f c11 open c12 0.1f clon 100pf c14 0.1f c15 0.1f c16 0.1f 24 23 22 21 20 19 7 8 9 10 11 12 cout 100pf vpos vpos qbbp qbbn ibbn ibbp exposed paddle clop 100pf lo gnd z1 f-mod 06511-025 figure 25. basic connections for the adl5372 power supply and grounding all the vps pins must be connected to the same 5 v source. adjacent pins of the same name can be tied together and decoupled with a 0.1 f capacitor. these capacitors should be located as close as possible to the device. the power supply can range between 4.75 v and 5.25 v. the com1 pin, com2 pin, com3 pin, and com4 pin should be tied to the same ground plane through low impedance paths. the exposed paddle on the underside of the package should also be soldered to a low thermal and electrical impedance ground plane. if the ground plane spans multiple layers on the circuit board, they should be stitched together with nine vias under the exposed paddle. the application note an-772 discusses the thermal and electrical grounding of the lfcsp in detail. baseband inputs the baseband inputs qbbp, qbbn, ibbp, and ibbn must be driven from a differential source. the nominal drive level of 1.4 v p-p differential (700 mv p-p on each pin) should be biased to a common-mode level of 500 mv dc. the dc common-mode bias level for the baseband inputs may range from 400 mv to 600 mv. this results in a reduction in the usable input ac swing range. the nominal dc bias of 500 mv allows for the largest ac swing, limited on the bottom end by the adl5372 input range and on the top end by the output compliance range on most dacs from analog devices. lo input a single-ended lo signal should be applied to the loip pin through an ac coupling capacitor. the recommended lo drive power is 0 dbm. the lo return pin, loin, should be ac-coupled to ground through a low impedance path. the nominal lo drive of 0 dbm can be increased to up to 6 dbm to realize an improvement in the noise performance of the modulator. this improvement is tempered by degradation in the sideband suppression performance (see figure 20 ) and, therefore, should be used judiciously. if the lo source cannot provide the 0 dbm level, then operation at a reduced power below 0 dbm is acceptable. reduced lo drive results in slightly increased modulator noise. the effect of lo power on sideband suppression and carrier feedthrough is shown in figure 20 . the effect of lo power on gsm noise is shown in figure 35 . rf output the rf output is available at the vout pin (pin 13). the vout pin connects to an internal balun, which is capable of driving a 50 load. for applications requiring 50 output impedance, external matching is needed (see figure 8 for s22 performance). the internal balun provides a low dc path to ground. in most situations, the vout pin should be ac-coupled to the load.
adl5372 rev. 0 | page 13 of 24 optimization the carrier feedthrough and sideband suppression performance of the adl5372 can be improved by using optimization techniques. carrier feedthrough nulling carrier feedthrough results from minute dc offsets that occur between each of the differential baseband inputs. in an ideal modulator, the quantities (v iopp ? v iopn ) and (v qopp ? v qopn ) are equal to zero, which results in no carrier feedthrough. in a real modulator, those two quantities are nonzero; and, when mixed with the lo, they result in a finite amount of carrier feedthrough. the adl5372 is designed to provide a minimal amount of carrier feedthrough. should even lower carrier feedthrough levels be required, minor adjustments can be made to the (v iopp ? v iopn ) and (v qopp ? v qopn ) offsets. the i-channel offset is held constant while the q-channel offset is varied until a minimum carrier feedthrough level is obtained. the q-channel offset required to achieve this minimum is held constant, while the offset on the i-channel is adjusted until a new minimum is reached. through two iterations of this process, the carrier feedthrough can be reduced to as low as the output noise. the ability to null is sometimes limited by the resolution of the offset adjustment. figure 26 shows the relationship of carrier feedthrough vs. dc offset as null. ? 60 ?88 ?84 ?80 ?76 ?72 ?68 ?64 ?300 ?240 ?180 ?120 ?60 0 60 120 180 240 300 06511-045 carrier feedthrough (dbm) v p ? v n offset (v) figure 26. carrier feedthrough vs. dc offset voltage at 1900 mhz note that throughout the nulling process, the dc bias for the baseband inputs remains at 500 mv. when no offset is applied v iopp = v iopn = 500 mv, or v iopp ? v iopn = v ios = 0 v when an offset of +v ios is applied to the i-channel inputs v iopp = 500 mv + v ios /2, and v iopn = 500 mv ? v ios /2, such that v iopp ? v iopn = v ios the same applies to the q channel. it is often desirable to perform a one-time carrier null calibra- tion. this is usually performed at a single frequency. figure 27 shows how carrier feedthrough varies with lo frequency over a range of 50 mhz on either side of a null at 1900 mhz. 06511-022 lo frequency (mhz) carrier feedthrough (dbm) ?80 ?75 ?70 ?65 ?60 ?55 ?50 ?45 ?40 ?35 ? 30 1850 1860 1870 1880 1890 1900 1910 1920 1930 1940 1950 figure 27. carrier feedthrough vs. frequency after nulling at 1900 mhz sideband suppression optimization sideband suppression results from relative gain and relative phase offsets between the i-channel and q-channel and can be suppressed through adjustments to those two parameters. figure 28 illustrates how sideband suppression is affected by the gain and phase imbalances. 0db 0.0125db 0.025db 0.05db 0.125db 0.25db 0.5db 1.25db 2.5db 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 0.01 0.1 1 10 100 sideband suppression (dbc) phase error (degrees) 06511-028 figure 28. sideband suppression vs. quadrature phase error for various quadrature amplitude offsets figure 28 underlines the fact that adjusting only one parameter improves the sideband suppression only to a point, unless the other parameter is also adjusted. for example, if the amplitude offset is 0.25 db, improving the phase imbalance better than 1 does not yield any improvement in the sideband suppression. for optimum sideband suppression, an iterative adjustment between phase and amplitude is required. the sideband suppression nulling can be performed either through adjusting the gain for each channel or through the modification of the phase and gain of the digital data coming from the digital signal processor.
adl5372 rev. 0 | page 14 of 24 applications information dac modulator interfacing the adl5372 is designed to interface with minimal components to members of the analog devices family of dacs. these dacs feature an output current swing from 0 to 20 ma, and the interface described in this section can be used with any dac that has a similar output. driving the adl5372 with a txdac? an example of the interface using the ad9779 txdac is shown in figure 29 . the baseband inputs of the adl5372 require a dc bias of 500 mv. the average output current on each of the outputs of the ad9779 is 10 ma. therefore, a single 50 resistor to ground from each of the dac outputs results in an average current of 10 ma flowing through each of the resistors, thus producing the desired 500 mv dc bias for the inputs to the adl5372. rbip 50 ? rbin 50? 93 92 19 20 out1_n out1_p ibbn ibbp ad9779 f-mod rbqn 50? rbqp 50? 84 83 23 24 out2_p out2_n qbbp qbbn 06511-029 figure 29. interface between the ad9779 and adl5372 with 50 resistors to ground to establish the 500 mv dc bi as for the adl5372 baseband inputs the ad9779 output currents have a swing that ranges from 0 to 20 ma. with the 50 resistors in place, the ac voltage swing going into the adl5372 baseband inputs ranges from 0 v to 1 v. a full-scale sine wave out of the ad9779 can be described as a 1 v p-p single-ended (or 2 v p-p differential) sine wave with a 500 mv dc bias. limiting the ac swing there are situations in which it is desirable to reduce the ac voltage swing for a given dac output current. this can be achieved through the addition of another resistor to the interface. this resistor is placed in the shunt between each side of the differential pair, as shown in figure 30 . it has the effect of reducing the ac swing without changing the dc bias already established by the 50 resistors. rbip 50? rbin 50? 93 92 19 20 ibbn ibbp ad9779 f-mod rbqn 50? rbqp 50? 84 83 23 24 rsli 100? rslq 100 ? out1_n out1_p out2_p out2_n qbbp qbbn 06511-030 figure 30. ac voltage swing reduction through the introduction of a shunt resistor between differential pair the value of this ac voltage swing limiting resistor is chosen based on the desired ac voltage swing. figure 31 shows the relationship between the swing-limiting resistor and the peak- to-peak ac swing that it produces when 50 bias-setting resistors are used. 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 10 100 1000 10000 differential swing (v p-p) r l ( ? ) 06511-031 figure 31. relationship between the ac swing-limiting resistor and the peak-to-peak voltage swing with 50 bias-setting resistors filtering it is necessary to low-pass filter the dac outputs to remove images when driving a modulator. the interface for setting up the biasing and ac swing that was discussed in the limiting the ac swing section lends itself well to the introduction of such a filter. the filter can be inserted between the dc bias setting resistors and the ac swing-limiting resistor. doing so establishes the input and output impedances for the filter.
adl5372 rev. 0 | page 15 of 24 an example is shown in figure 32 with a third-order, elliptical, low-pass filter with a 3 db frequency of 3 mhz. matching input and output impedances makes the filter design easier, so the shunt resistor chosen is 100 , producing an ac swing of 1 v p-p differential. rbip 50 ? rbin 50 ? 93 92 19 20 ibbn ibbp ad9779 f-mod rbqn 50 ? rbqp 50 ? 84 83 23 24 rsli 100? rslq 100 ? out1_n out1_p out2_p out2_n qbbp qbbn lpi 2.7nh lni 2.7nh 1.1nf c1i 1.1nf c2i lnq 2.7nh lpq 2.7nh 1.1nf c1q 1.1nf c2q 06511-032 figure 32. dac modulator interface with 3 mhz third-order, elliptical low-pass filter using the ad9779 auxiliary dac for carrier feedthrough nulling the ad9779 features an auxiliary dac that can be used to inject small currents into the differential outputs for each main dac channel. this feature can be used to produce the small offset voltages necessary to null out the carrier feedthrough from the modulator. figure 33 shows the interface required to use the auxiliary dacs. this adds four resistors to the interface. rbip 50 ? rbin 50? 93 90 92 19 20 ibbn ibbp ad9779 f-mod rbqn 50? rbqp 50? 84 87 89 83 86 23 24 rsli 100? rslq 100 ? out1_n aux1_n aux2_n out1_p aux1_p out2_p aux2_p out2_n qbbp qbbn lpi 2.7nh lni 2.7nh 1.1nf c1i 1.1nf c2i lnq 2.7nh lpq 2.7nh 1.1nf c1q 1.1nf c2q 250 ? 500 ? 500 ? 500 ? 500 ? 250 ? 250 ? 250 ? 06511-033 figure 33. dac modulator interface with auxiliary dac resistors gsm operation figure 34 shows the gsm evm, spectral mask, and noise vs. the output power for the adl5372 at 1960 mhz. for a given lo amplitude, the performance is independent of output power. 06511-026 output power (dbm) 250khz, 400khz, 600khz and 1200khz spectral mask (dbc/30khz) 6mhz offset noise floor (dbc/100khz) ?110 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ? 30 ?6 ?4 ?2 0 2 4 6 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 peak and rms evm (%) 6 mhz noise floor 1.2mhz peak evm 600khz 400khz 250khz rms evm figure 34. gsm evm and spectral performance vs. channel power at 1960 mhz vs. output power; lo power = 0 dbm figure 35 shows the gsm evm and noise performance vs. the lo amplitude at 1960 mhz with an output power of 5 dbm. increasing the lo drive level improves the noise performance but degrades evm performance. 06511-027 lo drive (dbm) peak and rms evm (%) 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 ?6 ?4 ?2 0 2 4 6 ?120 ?115 ?110 ?105 ?100 ?95 ?90 ?85 ? 80 6mhz offset noise floor (dbc/100khz) 6mhz noise floor rms evm peak evm figure 35. gsm evm and 6 mhz noise floor vs. lo power at 1960 mhz; output power = 5 dbm figure 35 illustrates that an lo amplitude of 3 dbm provides the ideal operating point for noise and evm for a gsm signal at 1960 mhz.
adl5372 rev. 0 | page 16 of 24 wcdma operation the adl5372 is suitable for operation in a wcdma environment, providing better than 72.5 db of adjacent channel power ratio (acpr) at an output power of ?10 dbm, with a 20 mhz noise floor of ?157 dbm/hz. figure 36 and figure 37 show the acpr and 20 mhz offset noise floor of the adl5372 vs. the output power at lo frequencies of 1966 mhz and 2140 mhz, respectively. 06511-034 p out (dbm) adjacent and alternate channel power ratios (db) ?14 ?13 ?12 ?11 ?10 ?9 ?8 ?7 20mhz offset noise floor (dbm/hz) adjacent cpr alternate cpr 20mhz noise floor ?82 ?80 ?78 ?76 ?74 ?72 ? 70 ?158.5 ?158.0 ?157.5 ?157.0 ?156.5 ?156.0 ? 155.5 figure 36. wcdma adjacent and alternate channel power ratios and 20 mhz offset noise floor vs. output power at 1966 mhz; lo power = 0 dbm 06511-035 p out (dbm) adjacent and alternate channel power ratios (db) ?14 ?13 ?12 ?11 ?10 ?9 ?8 ?7 20mhz offset noise floor (dbm/hz) adjacent cpr alternate cpr 20mhz noise floor ?82 ?80 ?78 ?76 ?74 ?72 ? 70 ?158.5 ?158.0 ?157.5 ?157.0 ?156.5 ?156.0 ? 155.5 figure 37. wcdma adjacent and alternate channel power and 20 mhz offset noise floor vs. output power at 2140 mhz; lo power = 0 dbm wimax operation figure 38 demonstrates the acpr vs. the output power for the adl5372 at 2350 mhz. the following test conditions were applied: a 10 mhz wide 64-qam ofdm signal with 256 subcarriers, and a raised cosine filter with an = 0.2. 06511-046 output power (dbm) acpr (db) ?72 ? 58 ?16 ?14 ?12 ?10 ?8 ?6 ?4 ?2 ?160 ? 153 70mhz offset noise floor (dbm/hz) ?70 ?68 ?66 ?64 ?62 ?60 ?159 ?158 ?157 ?156 ?155 ?154 acpr 70mhz offset noise floor figure 38. wimax acpr and noise floor vs. output power at 2350 mhz; lo power = 0 dbm lo generation using plls analog devices has a line of plls that can be used for generating the lo signal. table 4 lists the plls together with their maximum frequency and phase noise performance. table 4. analog devices pll selection table part frequency f in (mhz) phase noise @ 1 khz offset and 200 khz pfd (dbc/hz) adf4110 550 ?91 @ 540 mhz adf4111 1200 ?87 @ 900 mhz adf4112 3000 ?90 @ 900 mhz adf4113 4000 ?91 @ 900 mhz adf4116 550 ?89 @ 540 mhz adf4117 1200 ?87 @ 900 mhz adf4118 3000 ?90 @ 900 mhz the adf4360 comes as a family of chips, with nine operating frequency ranges. one is chosen, depending on the local oscillator frequency required. while the use of the integrated synthesizer may come at the expense of slightly degraded noise performance from the adl5372, it can be a cheaper alternative to a separate pll and vco solution. table 5 shows the options available. table 5. adf4360 family operating frequencies part output frequency range (mhz) adf4360-0 2400 to 2725 adf4360-1 2050 to 2450 adf4360-2 1850 to 2150 adf4360-3 1600 to 1950 adf4360-4 1450 to 1750 adf4360-5 1200 to 1400 adf4360-6 1050 to 1250 adf4360-7 350 to 1800 adf4360-8 65 to 400
adl5372 rev. 0 | page 17 of 24 transmit dac options the ad9779 recommended in the previous sections of this data sheet is by no means the only dac that can be used to drive the adl5372. there are other appropriate dacs, depending on the level of performance required. table 6 lists the dual txdacs offered by analog devices. table 6. dual txdac selection table part resolution (bits) update rate (msps minimum) ad9709 8 125 ad9761 10 40 ad9763 10 125 ad9765 12 125 ad9767 14 125 ad9773 12 160 ad9775 14 160 ad9777 16 160 ad9776 12 1000 ad9778 14 1000 ad9779 16 1000 all dacs listed have nominal bias levels of 0.5 v and use the same simple dac modulator interface that is shown in figure 32 . modulator/demodulator options table 7 lists other analog devices modulators and demodulators. table 7. modulator/demodulator options part no. modulator/ demodulator frequency range (mhz) comments ad8345 modulator 140 to 1000 ad8346 modulator 800 to 2500 ad8349 modulator 700 to 2700 adl5390 modulator 20 to 2400 external quadrature adl5385 modulator 50 to 2200 adl5370 modulator 300 to 1000 adl5371 modulator 500 to 1500 adl5373 modulator 2300 to 3000 adl5374 modulator 3000 to 4000 ad8347 demodulator 800 to 2700 ad8348 demodulator 50 to 1000 ad8340 vector modulator 700 to 1000 ad8341 vector modulator 1500 to 2400
adl5372 rev. 0 | page 18 of 24 evaluation board populated rohs-compliant evaluation boards are available for evaluation of the adl5372. the adl5372 package has an exposed paddle on the underside. this exposed paddle must be soldered to the board (see the power supply and grounding section). the evaluation board is designed without any components on the underside so heat can be applied to the underside for easy removal and replacement of the adl5372. vps5 vps3 vps4 vps2 vps2 vout com2 loin loip com2 com3 com3 qbbp com4 qbbn com4 ibbn ibbp com1 vps1 com1 vps1 vps1 vps1 vpos 1 2 3 4 5 6 18 17 16 15 14 13 vout c13 0.1f c11 open c12 0.1f clon 100pf c14 0.1f c15 0.1f c16 0.1f 24 23 22 21 20 19 7 8 9 10 11 12 cout 100pf l12 0 ? l11 0 ? vpos rfnq 0 ? rfpq 0 ? qbbp qbbn ibbn ibbp rfni 0 ? rfpi 0 ? cfnq open cfpq open cfpi open cfni open rti open rtq open exposed paddle clop 100pf lo gnd z1 f-mod 06511-036 figure 39. adl5372 evaluation board schematic 06511-037 figure 40. evaluation board layout, top layer table 8. evaluation board configuration options component description default condition vpos, gnd power supply and ground clip leads. not applicable rfpi, rfni, rfpq, rfnq, cfpi, cfni, cfpq, cfnq, rtq, rti baseband input filters. these components can be used to implement a low-pass filter for the baseband signals. see the filtering section. rfnq, rfpq, rfni, rfpi = 0 (0402) cfnq, cfpq, cfni, cfpi = open (0402) rtq, rti = open (0402)
adl5372 rev. 0 | page 19 of 24 characterization setup fmod test setup ip in qp qn out gnd vpos fmod lo i out q out vpos +5v lo output 90 0 iq r and s spectrum analyzer fsu 20hz to 8ghz i/am q/fm agilent 34401a multimeter 0.175 adc agilent e3631a power supply 5.000 0.175a com 6v 25v + ? + ? aeroflex ifr 3416 250khz to 6ghz signal generator rf out freq 4mhz level 0dbm bias 0.5v bias 0.5v gain 0.7v gain 0.7v connect to back of unit +6dbm rf in 0 6511-038 figure 41. characterization bench setup the primary setup used to characterize the adl5372 is shown in figure 41 . this setup was used to evaluate the product as a single-sideband modulator. the aeroflex signal generator supplied the lo and differential i and q baseband signals to the device under test, dut. the typical lo drive was 0 dbm. the i-channel is driven by a sine wave, and the q-channel is driven by a cosine wave. the lower sideband is the single sideband (ssb) output. the majority of characterization for the adl5372 was performed using a 1 mhz sine wave signal with a 500 mv common-mode voltage applied to the baseband signals of the dut. the baseband signal path was calibrated to ensure that the v ios and v qos offsets on the baseband inputs were minimized, as close as possible, to 0 v before connecting to the dut. see the carrier feedthrough nulling section for the definitions of v ios and v qos .
adl5372 rev. 0 | page 20 of 24 fmod test rack single to differential circuit board q in dccm agnd i in dccm vn1 vp1 i in ac q in ac vpos +5v lo 0 90 iq qp qn agilent 34401a multimeter 0.200 adc agilent e3631a power supply 5.000 0.350a com 6v 25v + ? + ? agilent e3631a power supply 0.500 0.010a com vcm = 0.5v 6v 25v + ? + ? r and s fsea 30 spectrum analyzer 100mhz to 4ghz +6dbm rf in tektronix afg3252 dual function arbitrary function generator 1mhz ampl 700mv p-p phase 0 1mhz ampl 700mv p-p phase 90 ch1 ch1 output ch2 output ch2 rf out r and s smt 06 signal generator freq 4mhz to 4ghz level 0dbm in1 in1 tsen gnd vposb vposa ip in ip in qp qn lo out output gnd vpos +5v vpos +5v ?5v fmod char bd 06511-039 figure 42. setup for baseband frequency sweep and undesired sideband nulling the setup used to evaluate baseband frequency sweep and undesired sideband nulling of the adl5372 is shown in figure 42 . the interface board has circuitry that converts the single-ended i input and q input from the arbitrary function generator to differential i and q baseband signals with a dc bias of 500 mv. undesired sideband nulling was achieved through an iterative process of adjusting amplitude and phase on the q-channel. see sideband suppression optimization section for a detailed discussion on sideband nulling.
adl5372 rev. 0 | page 21 of 24 outline dimensions * compliant to jedec standards mo-220-vggd-2 except for exposed pad dimension 1 24 6 7 13 19 18 12 * 2.45 2.30 sq 2.15 0.60 max 0.50 0.40 0.30 0.30 0.23 0.18 2.50 ref 0.50 bsc 12 max 0.80 max 0.65 typ 0.05 max 0.02 nom 1.00 0.85 0.80 seating plane pin 1 indicator top view 3.75 bsc sq 4.00 bsc sq pin 1 indicator 0.60 max coplanarity 0.08 0.20 ref 0.23 min exposed pa d (bottomview) figure 43. 24-lead lead frame chip scale package [lfcsp_vq] 4 mm 4 mm body, very thin quad (cp-24-2) dimensions shown in millimeters ordering guide model temperature range package descript ion package option ordering quantity adl5372acpz-r2 1 C40c to +85c 24-lead lfcsp_vq, 7 tape and reel cp-24-2 250 adl5372acpz-r7 1 C40c to +85c 24-lead lfcsp_vq, 7 tape and reel cp-24-2 1,500 adl5372acpz-wp 1 C40c to +85c 24-lead lfcsp_vq, waffle pack cp-24-2 64 adl5372-evalz 1 evaluation board 1 z = pb-free part.
adl5372 rev. 0 | page 22 of 24 notes
adl5372 rev. 0 | page 23 of 24 notes
adl5372 rev. 0 | page 24 of 24 t notes ?2006 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d06511-0-12/06(0) ttt

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